Ongoing trends in semiconductor device technology include miniaturization of a feature size of semiconductor devices as well as increasing functional complexity of semiconductor devices. Although a feature size reduction may facilitate an increase in the number of semiconductor building blocks per unit area of a semiconductor device, e.g. a die or an integrated circuit (IC), thus facilitating more complex functionality per device, many demands for the increased functional complexity cannot be met by a single device.
This has led to the development of aggregate devices such as three-dimensional integrated circuits (3D ICs). One example of creating a 3D IC is by building electronic components and their connections in layers on a single semiconductor wafer. As a base layer of the IC is formed on a substrate, a first upper layer is formed over the base layer and is connected to the base layer using vias. Another upper layer may be formed over the first upper layer, and so on. In this way, the IC is sequentially grown layer by layer. An IC thus built is generally known as a monolithic stacked IC (or a stacked IC).
Though promising in providing density and performance benefits in advanced process nodes, such as 28 nm and below, the fabrication of monolithic stacked ICs has its own challenges. One of the challenges is directed to manufacture yields of monolithic stacked ICs, which are compounded by multiplying yields of each layer of the stacked ICs. As each layer may contain manufacturing defects, such as opens, shorts, and out-of-spec components, a stacked IC suffers a low yield issue. Other challenges include heat dissipation and electromagnetic interference (EMI) as more and more layers containing analog circuits and digital circuits are stacked into one IC.